Programmable Logic Array (PLA)

Programmable Logic Array (PLA)


A programmable logic array (PLA) is a large Scale Integrated programmable logic device which is used for synthesizing combinational logic functions.  It consists of a programmable AND gate array followed by a programmable OR gate array. To synthesize the output logic functions, first of all these are needed to be reduced to their minimum sum of product expressions. In PLA implementation, a designer should try to deduce these expressions in such a way that maximum number of common product terms exist between them. All these product terms are then generated in the AND gate array. From there, these product terms are fed in to the OR gate array where they are added according to the deduced logic expressions in order to get the output functions.

Programmable Logic Array (PLA)

Both ROM and PLA can be used to implement arbitrary functions in the sum-of-product (SOM, actually OR-of-AND) form.


Example: Implement the following function by ROM and PLA: 

This function is implemented by ROM as the OR of five minterms: 

But after simplification by Karnaugh map:

the function can be implemented by a PLA as the OR of three terms:

Note that in a PLA, only those terms that are needed are generated by the AND array, while in a ROM, all minterms have to be generated by the AND array.